A finished gate structure (such as a finished gate or transistor gate) is the transistor terminal that modulates channel conductivity. Two principle approaches for forming semiconductor device gate structures are the gate-first and gate-last process approaches.
During fabrication of gate structures for, for instance, complementary metal-oxide-semiconductor (CMOS) technology, gate-first fabrication has traditionally been employed. In a gate-first fabrication approach, a conductor is provided over a gate dielectric, and then patterned (i.e., etched) to form one or more gate structures. After forming the gate structures, source and drain features of the semiconductor devices are provided.
More recently, the gate-last approach (or replacement metal gate (RMG) approach), has been employed. In the gate-last approach, a sacrificial (or dummy) gate material is provided and patterned (i.e., etched) to define one or more sacrificial gates. Some or all of the sacrificial gates are subsequently replaced with, for instance, a metal gate, after source and drain features of the devices have been formed. The sacrificial gate material holds the position for the subsequent metal gate to be formed. For instance, an amorphous silicon (a-Si) or polysilicon sacrificial gate may be patterned and used during initial processing until high-temperature annealing to activate the source and drain features has been completed. Subsequently, the a-Si or polysilicon may be removed and replaced with the final metal gate. Further, a semiconductor technology node scales down to nano-scale regime, it requires the parasitic capacitances to be small to improve device AC performance. The large parasitic capacitance associated with spacers is one of the key dielectrics which may degrade transistor performance. A Low-K spacer is a good candidate to minimize parasitic capacitance for high performance CMOS technology, and there may be less of an impact to the properties thereof induced by downstream processes In general, total overlap capacitance (Cov) consists of three components: direct overlap capacitance (Cdo), outer fringing capacitance (Cof), and inner fringing capacitance (Cif). As a channel length shrinks, the distances between a gate electrode to source/drain and contact fields also scale down and the direct effect is Cof becomes more prominent.
Accordingly, a need exists for improved systems and methods for forming semiconductor device gate structures to reduce parasitic losses.